(1) Field of the Invention
The present invention generally relates to a control system formed in a computer system having a plurality of processing modules and a plurality of shared memory modules, each of which processing modules has at least a main memory, a central processing unit and a connecting unit connected to a system bus, and each of which memory modules has at least a shared memory unit and a connecting unit connected to the system bus, and more particularly to a control system for controlling a process in which the processing modules exclusively access the shared memory modules.
(2) Description of the Prior Art
A computer system has been known, in which system a plurality of processing modules are coupled to a plurality of shared memory modules by system buses. Each system bus is controlled in accordance with, for example, a method referred to as a split method. By this method, activation transmission and response transmission are separately performed in an accessing operation between a processing module and a shared memory module coupled thereto by a system bus. In the period from the end of the activation transmission to the start of the response transmission, the system bus is released so that the system bus can be used by another processing module.
In the accessing operation in accordance with the above method, if the response transmission fails due to intermittent failure of the system bus, the system recognizes that the accessing operation has failed. The accessing operation is retried after the system bus is released to other processing modules.
In a case where a processing module exclusively accesses a shared memory module, the accessing processing module is informed of processing results, and it is necessary to rapidly deal with the failure of the accessing operation. Particularly, when the writing of information to the shared memory module fails, data in the shared memory module is damaged. Thus, the failure of the writing operation greatly affects the computer system.
In the system in which after the system bus is released to other processing modules, the accessing operation is retried, it is possible for another processing module to access the shared memory module in which the failure has occurred at a time when the system bus is released. Thus, there is a possibility that the failure of the writing operation in the shared memory module affects many processing modules in the system.